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type ordering code package fze 1658g q67000-a8361 p-dso-24-1 8 x digital sensor interface p-dso-24-1 features l input protection against 2000 v burst/500 v surge pulse according to iec 801 4/5 l input characteristic according to iec 65 a, type 2 (24 v dc) l digital filter l serial in/out for easy cascading l low power dissipation l smd package semiconductor group 1 01.97 fze 1658g the fze 1658g is an integrated interface for digital sensors - i.e. proximity switches - in industrial automation equipment. the ic has eight integrated highly protected and failsafe inputs with status led and a serial synchronous output for direct mc-interfacing.
fze 1658g semiconductor group 2 pin configuration (top view)
fze 1658g semiconductor group 3 pin definitions and functions pin symbol function 15, 13, 11, 9, 5, 3, 1, 23 i0 - i7 inputs for 24-v signals, in conjunction with r v and r ext current sink characteristic. 16, 14, 12, 10, 6, 4, 2, 24 l0 - l7 outputs for the status leds; led lights when h-signal is present at input. 21 ct pin for connecting the frequency-determining capacitor for the filter clock; also reset input if ct is connected to dgnd . 7 gnd ground for all 24-v signals, substrate. 22 dgnd ground for all 5-v signals, no internal connection to gnd. any interruption of gnd or dgnd with the supply voltage present may result in destruction of the device. 8 v s supply voltage; undervoltage activates internal reset. 20 so-n serial output, open drain. 17 se-n extention input for serial cascading with pull-up current source. 18 lo-n latch input, edge h-l results in transfer of data from the digital filters to the output register. 19 t clock for serial output, positive edge triggered.
fze 1658g semiconductor group 4 functional description and application the integrated circuit fze 1658g is used to detect the signal states of eight independent input lines according to iec 65a type 2 (e.g. two-wire proximity switches) with a common ground (gnd). for operation in accordance with iec 65a, it is necessary for the device to be wired with resistors rated r v = 820 w and r ext = 4.4 k w with 2% tolerance and 200 ppm tk. the input device has the following characteristics: C minimization of power dissipation due to constant current characteristic C inputs protected against reverse polarity and transient overvoltages C status led output for each input C digital averaging of the input signals to suppress interference pulses C serial output of the detected signals (cascadable) maximum voltage ratings at inputs d0 ... d7 within test circuit 2. the rated voltage may be applied to all inputs simultaneously. the values given in the table may be regarded as guaranteed, but are only checked as part of a qualification (no 100 % series testing). within the application circuit given the same voltage ratings as above apply for the supply line. 1) non-destructive in temperature range 15 c t a 35 c. 2) in temperature range 15 c t a 35 c: data retained if the supply voltage remains within the operating range; without supply voltage non-destructive. voltage range notes dc voltage C 3 v + 32 v C32v +32v full function non-destructive, no latch-up overvoltage 500 ms C 3 v + 35 v C35v +35v full function non-destructive, no latch-up overvoltage 1.3 ms to vde 0160 C 3 v + 55 v 55 full function non-destructive, no latch-up surge pulse 50 m s to iec 801-5, z i = 2 w 0.5 kv 1) burst pulse 50 ns to iec 801-4, z i = 50 w 2kv 2)
fze 1658g semiconductor group 5 circuit description in iec 65a, the following values are specified for 24-vdc input stages of type 2: the current in the input circuit is determined by the switching element in state 0 and by characteristics of the input stage in state 1. the octal input device fze 1658g is intended for a configuration comprising two specified external resistors per channel, as shown in the block diagram. as a result the power dissipation within the p-dso-24-1 package is at a minimum. the voltage dependent current through the external resistor r ext is compensated by a negative differential resistance of the current sink across pins e and l, therefore input d behaves like a constant current sink. the comparator assigns level 1 or 0 to the voltage present at input e. to improve interference protection, the comparator is provided with hysteresis and a delay element. a status led is connected in series with the input circuit ( r ext and current sink). the led drive short-circuits the status led if the comparator detects 0. a constant current sink in parallel with the led reduces the operating current of the led, and a voltage limiter ensures that the input circuit remains operational if the led is interrupted. the specified switching thresholds may change if the led is interrupted. for each channel a digital filter is provided which samples the comparator signal at a rate provided by the clock oscillator. the digital filter is designed as a 5-section shift register. if any four out of 5 sampling values are identical, the output s changes to the corresponding state. on a falling edge at input lo-n, the parallel data s0 - s7 are clocked into the output shift register. the data can be shifted out serially to the output so-n by the clock signal t, with a 1 at the input being represented by a l-signal at the output so-n. the serial interface of the shift register fits the synchronous interface of the 8051 microcontroller ( see diagram serial data output function ). by connecting output so-n to input se- n of the next device, several fze 1658g can be cascaded ( see application circuit ). so-n is designed as an open-drain output. se-n has an internal pull-up current source. inputs se-n, t and so-n have schmitt trigger characteristics. the device has separate ground pins for the input circuitry (gnd) and for the logic (dgnd). if the supply voltage falls below v usr or ct is connected to dgnd, the output shift register will be cleared and the output so-n disabled. if the supply voltage is too low, the led drives will also be disabled, i.e. the led lights as soon as current flows in the input circuit. level input voltage input current 1 0 min. 11 v max. 11 v or max. 5 v min. 6 ma max. 2 ma
fze 1658g semiconductor group 6 block diagram
fze 1658g semiconductor group 7 absolute maximum ratings t j = C 40 to 150 c parameter symbol limit values unit notes min. max. transient input current inputs i0 - i7 i i C 0.6 C 1.2 C 2.5 0.6 1.2 2.5 a a a t 50 % 50 m s t 50 % 1.2 m s t 50 % 50 ns ground current i gnd C5 C10 5 10 a a t 50 % 50 m s t 50 % 50 ns junction temperature t j C 40 150 c storage temperature t s C 50 125 c thermal resistance system/air r thja 95 k/w soldered-in transient thermal resistance; same current through all inputs i0 - i7 z th z th 0.15 0.4 k/w k/w 50 m s pulse 120 m s pulse supply voltage v s C 0.3 65 v ground offset dgnd to gnd v dgnd C4 4 v v dgnd < v s current at the led outputs i l C15 C 500 C 250 C 125 15 500 250 125 ma ma ma ma t 50 % 50 m s t 50 % 1.2 m s t 50 % 50 m s voltage at t, lo-n, so-n, se-n v log C4 C 0.3 9 9 v v referred to dgnd capacitance at ct c ct 2 m f when v s falls below v ct esd voltage 100 pf / 1.5 k w v esd 1000 1000 v mil std. 883 meth. 3015 all voltages are, unless otherwise specified, referred to gnd. this also applies to the operating range and the characteristics.
fze 1658g semiconductor group 8 1) input voltages may rise before the supply voltage. full function at v s > v vsro (see characteristics). 2) limits gnd potential difference at minimum supply voltage. 3) also applies to several cascaded fze 1658g (note dependence with clock frequency). for definition of timing items, see timing diagram. operating range parameter symbol limit values unit notes min. max. supply voltage v s 10 48 v note power dissipation 1) supply voltage rise sr vs C 0.1 1 v/ m s supply voltage v s - v dgnd 9v 2) gnd potential difference v dgnd C 1.5 1.5 v input terminal current i it C10 10 ma input voltage se-n, t, lo-n v ih v il 2.8 C 0.5 6 1.7 v v input current se-n, t, lo-n i i C 1 1 ma clamp current junction temperature t j C 25 150 c ambient temperature t a C 25 105 c dependent on r th clock frequency f t 1 mhz clock pulse width h or l t th , t tl 300 ns se-n set up time to t - t vse 300 ns lo-n set up time to t - t vlo 1.2 m s se-n, lo-n, t rise and fall time within thresholds t r , t f 3 m s 3)
fze 1658g semiconductor group 9 characteristics v s = 15 v to 30 v; v dgnd = 0, t j = C 25 c< t j < 125 c parameter symbol limit values unit test condition test circuit min. typ. max. inputs i0 - i7 or d0 - d7 respectively switching threshold h v dh 10.85 1) v2 switching threshold l v dl 8v v l 2.2 v 2 hysteresis v dhy 1v v l 2.2 v 2 switching threshold l i dll 2.5 ma i led = 0 2 input current i dh 6.2 1) 8ma v l 3.5 v, v d = 11 30 v 2 input current i dl 57ma v l = v ll , v d = 5 v 2 input current i ic + 1ma v i = 30 v 2) 1 input clamp voltage v it + 35 75 v i i = 10 ma, t j = 25 c 2) 1 input current i ic C C1 ma v i = C 30 v 2) 1 input clamp voltage v it C C 75 C 35 v i i = C 10 ma, t j = 25 c 2) 1 1) headroom to iec 65 a for tolerance of ext. resistor. 2) also valid at v s = 0.
fze 1658g semiconductor group 10 led drive l0 - l7 open-load voltage v lo 3.5 5 v v d = 24 v, i led = 0 2 low- voltage v ll 0 0.75 v v d = 5 v, i led = 0 2 output current i led 35ma v d = 11 30 v, v l = 1.5 3 v 2 output current i led 1.5 6 ma v d = 11 30 v, v l = 1.2 3.5 v 2 power down output current i l C 0.12 ma v s < v vsru 1 propagation delay rising and falling edge t dl 7.5 75 m s v d = 12 v ? ? 7v 2 oscillator ct source/sink current i ct 150 250 m a1 frequency f ct 1 1.5 khz c t = 39 nf 2 upper switching threshold v ctp 3.3 4.3 v 2 lower switching threshold v ctn 1.4 2.2 v 2 reset threshold v ctr 0.8 1.4 v 1 reset input current i ctr C 300 C 150 m a v ct = 0.8 v 1 signal delay t dfi 24ms c t = 39 nf 2 characteristics (contd) v s = 15 v to 30 v; v dgnd = 0, t j = C 25 c< t j < 125 c parameter symbol limit values unit test condition test circuit min. typ. max.
fze 1658g semiconductor group 11 5-v logic input current t, lo-n i i C10 10 m a v i = 0 5 v 1 input current se-n i ise C 600 C 400 m a v i = 0 3 v 1 input current t, lo-n, se-n i i0 020 m a v i = 0 5 v v s = 0 v 1 input capacitance c i 10 pf 1 l-output current so-n i sol 5.5 8 ma v q = 3 5 v 1 l-output level so-n v sol 0 0.5 v i so = 2 ma 1 h-leakage current so-n i soh 050 m a v so = 5 v 1 output capacitance so-n c soh 20 pf v so = 1.5 v 1 rise/fall time of output current so-n t rso , t fso 50 ns v so = 2.5 v 1 delay time t to so-n (see timing diagram) t sot 150 ns v so = 2.5 v 1 delay time lo-n to so-n (see timing diagram) t solo 300 ns v so = 2.5 v 1 hysteresis se-n, lo-n 60 mv no 100% testing characteristics (contd) v s = 15 v to 30 v; v dgnd = 0, t j = C 25 c< t j < 125 c parameter symbol limit values unit test condition test circuit min. typ. max.
fze 1658g semiconductor group 12 hysteresis clock input 200 mv no 100% testing voltage supply current drain static i s 25ma v s = 10 30 v v lo-n = 5 v v t = 5 v i se-n = 0 2 current drain during serial readout i s 26ma v s = 10 40 v v lo-n = 0 v f t = 1 mhz 2 current drain during high supply voltage i smax 7ma v s < 45 v 2 logic ground current i dgnd C 2.5 0 ma v dgnd = C 1.5 1.5 v, lo-n = h 1 under voltage lockout v vsro v vsru v vsrh 8 0.2 10 v v v upper switching treshold lower switching threshold hysteresis 2 2 2 characteristics (contd) v s = 15 v to 30 v; v dgnd = 0, t j = C 25 c< t j < 125 c parameter symbol limit values unit test condition test circuit min. typ. max.
fze 1658g semiconductor group 13 test circuit 1 test circuit 2
fze 1658g semiconductor group 14 application circuit supply voltage decoupling circuit cascading multiple fze 1658g
fze 1658g semiconductor group 15 serial data output function
fze 1658g semiconductor group 16 timing diagram
fze 1658g semiconductor group 17 input characteristic with worst-case values per iec 65a input d rest circuit d
fze 1658g semiconductor group 18 package outlines gps05144 plastic-package, p-dso-24-1 (smd) (plastic dual small outline package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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